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When the power from 10 feet to send the output positive pulse input NAND gate IC3 and its output by 1 foot by 56 foot into a parallel non-inverting gate after the 4-pin output to IC1 and IC4 start automatically Jing ... 0. Meanwhile, the other input of NAND gate 2 feet by the count pulse to 16 o'clock, IC4 pin 11 output is formed after the transition by Differential \. ~ IIC4 and two counter synchronous operation. Therefore, the cycle monitor device synchronization cleared once a week per cycle, no accumulation of errors, strong anti-interference ability. Commissioning, in addition to the aforementioned pulse cycle count should be adjusted outside the periphery of the oscillating components IC1 W1, C2 should be adjusted to the time constant and oscillation frequency with IC2. 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